Field of the Invention
The present invention relates to a drive circuit for a non-volatile semiconductor storage configuration. The drive circuit has a level converter circuit which applies an output value and an output value complementary to this output value to a bit line and/or a word line of the semiconductor storage configuration and has a latch circuit (latch) which lies between an input circuit and the level converter circuit which temporarily stores the data to be stored in the semiconductor storage configuration.
Such a drive circuit is known from Published, European Patent Application EP 0 154 379 A2.
In order to add or remove charges, and therefore data, from the individual storage cells, non-volatile semiconductor storage configurations, for example flash memories and electrically erasable programmable read-only memories (EEPROM) require voltages typically of 15 V. These voltages, which are substantially higher than the normal supply voltage Vdd, which is of the order of 5 V, will also be referred to as "high voltages" below. Depending on the mode of operation, the high voltages are applied to word lines or bit lines, or to word lines and bit lines of a semiconductor storage configuration.
A stacked gate cell has a source region and a drain region in a semiconductor substrate. The source region and the drain region are both n.sup.+ -doped, while the semiconductor substrate has p-type doping. The source region and the drain region as well as the channel area of the semiconductor substrate between the source region and the drain region, are provided with a tunneling oxide layer of, for example, silicon dioxide. On the tunneling oxide layer, in the area between the drain region and the source region, there is a floating gate of, for example, polycrystalline silicon. On the floating gate, an interpoly dielectric and a control gate are further disposed.
In order to erase and program data, so-called "Fowler-Nordheim Tunneling" (FN tunneling) can be used in such a stacked gate cell. In an erasing process, for example 0 V is applied to the drain region and +15 V to the control gate. Electrons then tunnel from the channel area through the tunneling oxide layer into the floating gate. When programming, for example 0 V is applied to the control gate and +15 V to the drain region, which makes electrons tunnel from the floating gate through the tunneling oxide layer into the drain region. It is, however, also possible to apply, for example, -11 V to the control gate and +4 V to the drain region for programming. This also causes electrons to tunnel from the floating gate into the drain region.
When programming with hot electrons (hot e programming), for example +15 V is applied to the control gate, +5 V to the drain region and 0 V to the source region. As a result, electrons migrate from the drain region to the source region, and at the same time tunnel through the tunneling oxide layer into the floating gate.
It is known that an EEPROM can be programmed and erased bytewise, while a flash memory can be programmed bytewise using hot electrons or FN tunneling, and erased blockwise by FN tunneling.
As an example of another type of storage cell, a so-called split gate cell having the semiconductor substrate, the n.sup.+ -doped source region, the n.sup.+ -doped drain region, the tunneling oxide layer, the floating gate, the interpoly dielectric and the control gate. The "lowered" part of the control gate is also referred to as a series gate, since the raised control gate and the series gate can be regarded as interconnected gates of two NMOS transistors connected in series.
Storage cells of the above-mentioned type can form a semiconductor memory having bit lines BL0 word lines.
In a semiconductor storage configuration, it is necessary to be able to apply high voltages selectively to chosen word lines or bit lines, in order to erase or program individual storage cells. Besides semiconductor storage configurations, however, it is also necessary for specially regulated voltages with greater consistency than the supply voltage to be switched by high voltages of, for example, 15 V.
One important application is, for example, the driving of the bit lines in flash memories with negative programming voltage (see e.g. R. Heinrich, W. Heinrigs, G. Tempel, J. Winnerl, T. Zettler, in Proc. of the International Electron Device Meeting (IEDM), 1993, pages 445 to 448). In order to achieve constant programming conditions, the bit line voltage is, for example, regulated to 5 V in this case while -12 V is applied to the word lines. Such regulated voltages of, for example, 5 V, which lie below the supply voltage of 5.5 V, will also be covered below by the term "high voltage".
In order to produce such drive voltages, it is necessary to have a drive circuit that is to deliver the desired voltages with a high level of consistency and at the same time requiring little space.
Specifically, U.S. Pat. No. 5,293,761 describes a drive circuit having a voltage divider circuit for separately supplying the memory array and memory for a redundant configuration with high voltages. The known drive circuit has, in particular, a level converter circuit which makes it possible to apply an output value, and an output value complementary to the output value, to a semiconductor storage configuration.
It has, however, been shown that the known drive circuit according to U.S. Pat. No. 5,293,561 is unsuitable for driving bit lines since it does not allow any temporary storage of data. Further, the known drive circuit contains NMOS transistors of the depletion type which, as additional components, entail considerable technical complexity.
In contrast, the drive circuit according to Published, European Patent Application EP 0 154 379 A2 contains a large number of PMOS transistors, which have a relatively large area requirement and a low current yield.